Mufeng Chen

West Lafayette, IN, USA

chen5240 [at] purdue.edu

I am a Ph.D. student in Electrical and Computer Engineering at Purdue University, advised by Prof. Haitong Li in the NanoX Lab. I work on memory-centric computer architecture and circuits — building memory that does more than store, and rethinking the hierarchy around it once it does.

My work runs along two threads.

Analog hybrid memory systems

Single-technology memory forces a hard trade-off between density, endurance, and retention. I design mixed-signal macros that fuse complementary technologies into one array — eDRAM for fast decoupled read/write, RRAM for non-volatile density, and BEOL oxide-semiconductor FETs for retention — so that the trade-off becomes a design knob rather than a constraint.

The circuits only matter if the algorithms above them change too, so this thread is co-designed with the workload: RRAM-assisted multi-level programming paired with zeroth-order optimization for on-device LLM fine-tuning, floating-point dataflows that avoid alignment-induced accuracy loss, and hyperdimensional / vector-symbolic representations that make on-chip learning cheap.

HBF + X

High-Bandwidth Flash (HBF) puts NAND capacity inside the package at HBM-like bandwidth. That is a genuinely new tier in the hierarchy, not a faster SSD — and a tier behaves differently from a device. NAND page granularity, address mapping, background work, and queueing do not disappear just because the bandwidth is there. I am interested in what has to change above and below that tier:

The HBF–accelerator interface. HBM offers an implicit load/store contract that HBF cannot honor unchanged. What the interface should expose — and what it should hide — decides whether the capacity is usable or merely present.
HBF as a distinct tier. Which state actually belongs in flash: large, read-mostly, revisited after a gap. Placement and replacement policies written for a two-level hierarchy do not transfer cleanly to a three-level one.
Pooling HBF across accelerators. Package-level capacity is stranded if it is private to one GPU. Sharing a flash tier across accelerators raises questions of coherence, allocation, and interference that the single-device case never poses.

The X is where this thread meets the first one: the HBF base die is real silicon that can host control and compute, so the same near-memory and in-memory techniques become available one level down in the hierarchy.

Before Purdue, at Zhejiang University I led the RRAM-eDRAM hybrid CiM design group under Prof. Er-Ping Li, covering SNN-based vision models, system-level specification, parts of the digital design, and the heterogeneous-integration issues that come with fused memory. I interned at SIMS Lab (Prof. Kaiyuan Yang, Rice) in summer 2022 on charge-domain CiM, and at NanoX Lab (Prof. Haitong Li, Purdue) in summer 2023 on hyperdimensional computing.

I received my B.S. from the Department of Optics and Electronic Engineering at Huazhong University of Science and Technology, where I worked on silicon photonics, machine learning, and inverse design.

news

Aug 01, 2026	PROTEUS, our 40 nm programmable general-purpose digital CiM accelerator, is available in early access at IEEE JSSC. [paper]
Apr 01, 2026	Presented Heterogeneous Compute-in-Memory Fabrics for Efficient, Scalable Edge Inference and Learning at ISQED 2026. [paper]
Nov 01, 2025	CENTAUR, a 38.5-TFLOPS/W floating-point digital CiM engine, presented at IEEE A-SSCC 2025. [paper]
May 21, 2025	Presented Analog Multilevel eDRAM-RRAM CIM for Zeroth-Order Fine-tuning of LLMs at IEEE IMW 2025 in Monterey, CA. [paper]
Aug 19, 2024	Started my Ph.D. in Electrical and Computer Engineering at Purdue University, joining the NanoX Lab.

selected publications

JSSC
PROTEUS: A 40 nm Programmable General-Purpose Digital Compute-In-Memory Accelerator With eNVM and Hierarchical ISA for Versatile Edge AI

Luqi Zheng, Amir Massah Bavani, Mufeng Chen, and 11 more authors

IEEE Journal of Solid-State Circuits, 2026

Early Access

Abs DOI Bib HTML PDF

PROTEUS is an 18 mm2 programmable general-purpose digital compute-in-memory (GP-DCIM) accelerator integrating 4 Mb RRAM and 2.6 Mb tensor SRAM with a 32-bit hierarchical DCIM instruction set architecture, fabricated in 40 nm ultra-low-power CMOS with foundry RRAM. Fine-grained 1-D matrix tiling and a reconfigurable DCIM datapath/pipeline achieve near-100% memory utilization across INT8/INT16/FP8/FP16 computations. PROTEUS unifies SRAM/RRAM dataflows and embeds nonvolatile micro-programs in RRAM, enabling rapid switching among pre-stored kernels without off-chip instruction feeds or RRAM rewrites. The chip delivers 702 GOPS throughput, 6.4 TOPS/W energy efficiency, and 0.039 TOPS/mm2 compute density, validated on ResNet-20, BERT-Tiny, MobileViT, GraphSAGE, and Vision Mamba.
@article{zheng2026proteus, title = {PROTEUS: A 40 nm Programmable General-Purpose Digital Compute-In-Memory Accelerator With eNVM and Hierarchical ISA for Versatile Edge AI}, author = {Zheng, Luqi and Bavani, Amir Massah and Chen, Mufeng and Du, Shuting and Hsin, Te-Yu and Khwa, Win-San and Wu, Ping-Sheng and Lele, Ashwin Sanjay and Zhang, Bo and Crafton, Brian and Chuang, Harry and Chih, Yu-Der and Chang, Meng-Fan and Li, Haitong}, journal = {IEEE Journal of Solid-State Circuits}, year = {2026}, note = {Early Access}, doi = {10.1109/JSSC.2026.3694285}, }
A-SSCC
CENTAUR: A 38.5-TFLOPS/W 600MHz Floating-Point Digital Compute-In-Memory Engine with 40nm Fusion RRAM-eDRAM Macros Featuring 3D-MAC Operation

Luqi Zheng, Amir Massah Bavani, Shuting Du, and 8 more authors

In 2025 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2025

Abs Bib HTML PDF

Existing NVM-based floating-point CIM macros face significant area and energy overhead from integer/FP conversion or large pre-alignment logic, accuracy degradation from row-wise pre-alignment of weights, and limited operating frequency constrained by slow NVM sensing. CENTAUR is a floating-point CIM engine featuring RRAM-eDRAM fusion macros and a novel FP 3D-MAC dataflow that eliminates alignment-induced accuracy loss, reduces area overhead, and enables high-speed, energy-efficient FP computation. Fabricated in 40 nm CMOS with foundry RRAM, CENTAUR achieves 600 MHz operation and 38.5 TFLOPS/W, running Tiny-ViT on CIFAR-10 with only 1.75% accuracy degradation versus the software baseline.
@inproceedings{zheng2025centaur, title = {CENTAUR: A 38.5-TFLOPS/W 600MHz Floating-Point Digital Compute-In-Memory Engine with 40nm Fusion RRAM-eDRAM Macros Featuring 3D-MAC Operation}, author = {Zheng, Luqi and Bavani, Amir Massah and Du, Shuting and Hsin, Te-Yu and Chen, Mufeng and Khwa, Win-San and Lele, Ashwin and Chuang, Harry and Chih, Yu-Der and Chang, Meng-Fan and Li, Haitong}, booktitle = {2025 IEEE Asian Solid-State Circuits Conference (A-SSCC)}, year = {2025}, }
IMW
Analog Multilevel eDRAM-RRAM CIM for Zeroth-Order Fine-tuning of LLMs

Mufeng Chen, Luqi Zheng, Jheng-Yu Lin, and 2 more authors

In 2025 IEEE International Memory Workshop (IMW), 2025

Abs DOI Bib HTML PDF

Zeroth-order fine-tuning eliminates explicit back-propagation and reduces memory overhead for large language models, making it a promising approach for on-device fine-tuning. However, existing memory-centric accelerators fail to fully leverage these benefits due to inefficiencies in balancing bit density, compute-in-memory capability, and the endurance-retention trade-off. We present a reliability-aware, analog multi-level-cell eDRAM-RRAM compute-in-memory solution co-designed with zeroth-order optimization for language model fine-tuning. An RRAM-assisted eDRAM MLC programming scheme is developed, along with a PVT-robust, large-sensing-window time-to-digital converter. The MLC-eDRAM integrating two-finger MOM provides 12x improvement in bit density over state-of-the-art MLC designs, with another 5x density and 2x retention benefit from BEOL In2O3 FETs.
@inproceedings{chen2025analog, title = {Analog Multilevel eDRAM-RRAM CIM for Zeroth-Order Fine-tuning of LLMs}, author = {Chen, Mufeng and Zheng, Luqi and Lin, Jheng-Yu and Ye, Peide D. and Li, Haitong}, booktitle = {2025 IEEE International Memory Workshop (IMW)}, pages = {1--4}, year = {2025}, doi = {10.1109/IMW61990.2025.11026966}, }