Fused analog eDRAM-RRAM CiM
Mixed-signal macros that escape the density / endurance / retention trade-off
Analog multi-level-cell eDRAM-RRAM compute-in-memory co-designed with zeroth-order optimization for on-device LLM fine-tuning.
- An RRAM-assisted eDRAM MLC programming scheme, paired with a PVT-robust, large-sensing-window time-to-digital converter.
- MLC-eDRAM integrating a two-finger MOM capacitor, giving 12x better bit density than state-of-the-art MLC designs.
- BEOL In2O3 FETs contributing another 5x density and 2x retention benefit.
Published at IEEE IMW 2025, and extended in the CENTAUR floating-point CiM engine (A-SSCC 2025) and the PROTEUS general-purpose accelerator (JSSC).